As the global semiconductor industry enters the so-called 2-nanometer process era, the actual size of transistors—the core components of semiconductor chips—still remains above 10 nm. How much smaller, then, can transistors get? KAIST researchers have developed a technology to predict that limit through quantum mechanical, atom-level calculations.
A team led by Professor Yong-Hoon Kim of the School of Electrical Engineering has developed a computational design technology that uses computer simulations to analyze and predict the scaling limits of transistors, a key challenge in developing next-generation semiconductor devices. The work is published in the journal npj Computational Materials.
To read more, click here.