Building chips from collapsing nanopillars

The manufacture of nanoscale devices — the transistors in computer chips, the optics in communications chips, the mechanical systems in biosensors and in microfluidic and micromirror chips — still depends overwhelmingly on a technique known as photolithography. But ultimately, the size of the devices that photolithography can produce is limited by the very wavelength of light. As nanodevices get smaller, they’ll demand new fabrication methods.

In a pair of recent papers, researchers at MIT’s Research Laboratory of Electronics and Singapore’s Engineering Agency for Science, Technology and Research (A*STAR) have demonstrated a new technique that could produce chip features only 10 nanometers — or about 30 atoms — across. The researchers use existing methods to deposit narrow pillars of plastic on a chip’s surface; then they cause the pillars to collapse in predetermined directions, covering the chip with intricate patterns.

Ironically, the work was an offshoot of research attempting to prevent the collapse of nanopillars. “Collapse of structures is one of the major problems that lithography down at the 10-nanometer level will face,” says Karl Berggren, the Emanuel E. Landsman (1958) Associate Professor of Electrical Engineering and Computer Science, who led the new work. “Structurally, these things are not as rigid at that length scale. It’s more like trying to get a hair to stand up. It just wants to flop over.” Berggren and his colleagues were puzzling over the problem when, he says, it occurred to them that “if we can’t end up beating it, maybe we can use it.”